S & D Engineering Solutions

Job #10411

SR Verification Engineer

Contractor will be doing to following tasks:
Developing OVM Testbench components for LDPC Decoders & Flash Controllers  .
Writing up Detailed Verification Plans for the verification of LDPC Decoders to encapsulate Functional Coverage.
Developed Master & Slave Monitors, Sequence Items , Drivers for LDPC Soft Decoding IP
Setting up Assertions in testbenches ,transaction objects , developing Virtual Interfaces, debugging OVM Environment 
Debugging waveforms & testbenches with Cadence Simvision , debugging waveforms.
System C Modelling of Flash Channel  Worked on the development of Non Blocking Transport  mechanism, debugging
SystemC transactions with Mentor Vista .

 Skills/Experience
-  Strong knowledge of Verilog, SystemVerilog/OVM or Specman, SystemC.
-  At least 3 years of logic design.
-  C/C++ and scripting languages
-  Digital Simulation and Verification tool suite.

Additional experience in these areas is a plus:
  - Verification of digital signal processing data path
  - Error correction
  - Flash or magnetic storage read/write channel and controller design or application
  - Cadence Incisive Enterprise Simulator or equivalent platforms

Job 10411-2

Contractor will develop new features for Intel SSD (Solid State Drive Firmware/Micro-Controller), mostly around adding and validating new ATA commands.

Required:
1)     SATA/ATA host interface Firmware experience * 1 year+
2)     Firmware development experience * 5+ years
3)     C Programming * 5+ years
4)     SATA analyzer usage

 Preferred:
1)     SMART experience
2)     Python scripting